Logic functions are implemented using integrated circuit (IC) technology such as large scale integration (LSI). An integrated circuit package includes a chip, on which the logic functions are implemented, a plurality of pins and an architecture known as output structures, among other integrated logic components on the chip. The output structures are coupled to the pins to transfer logic signals from the chip via the pins to other IC packages.
A class of chips has been developed which are known as field-programmable logic families. The logic families are "field-programmable", which means that these chips can be programmed or modified by the chip users or purchasers with the aid of readily available programming equipment to change the logic, as desired. For example, one member of this logic class is the field-programmable logic sequencer whose output structures include built-in registers and combinatorial or non-registered logic. The output signals of the registers are known as stored or registered signals or outputs, whereas the output signals of the combinatorial logic are known as non-stored or non-registered signals. Specifically, the combinatorial logic can be programmed to provide non-inverted non-registered signals or inverted non-registered signals.
One disadvantage with the prior field-programmable logic families is that they have fixed numbers or combinations of registers and combinatorial logic gates. For example, one logic sequencer may have four registers whose signal outputs are connected to four pins, respectively, and eight combinatorial logic gates whose signal outputs are connected to eight pins, respectively. Another logic sequencer may have six registers and a like number of combinatorial logic gates whose signal outputs are connected, respectively, to twelve pins. However, a user or purchaser may need only three registers or five registers, thereby resulting in an inefficient or lack of use of register resources and pins since the purchased logic sequencer will have four or six registers, respectively, connected to a like number of pins. In other words, a user or purchaser may not be able to utilize efficiently a logic sequencer with the exact number of registers and pins needed. Furthermore, a given logic sequencer may not implement a given logic function should more registers be needed than are available on such a sequencer. Also, a user would need to purchase a variety of different logic sequencers to cover all applications, which increases inventory and production costs.
Another disadvantage of the prior logic sequencers is that each register and each combinatorial logic gate is dedicated or coupled to a particular pin, respectively. This can present problems related to the lay-out of the logic circuit on the chip. For example, it may be more space-saving or otherwise advantageous to have a given register laid out near an upper part of the chip, but the dedicated nature of the chip to the user or purchaser may contrain the location of the given register near a pin at the middle or lower portion of the chip.
The present invention is directed to overcoming all of the problems mentioned above.